The present invention relates to, for example, a NAND flash memory, and more particularly to a semiconductor memory device which can store multi-bit data.
In a NAND flash memory, all of the cells which are parallel in a row direction or half the number of cells are connected to a read/write latch circuit through respective bit lines. A write or read operation is collectively performed with respect to all of the cells which are parallel in a row direction or half the number of cells (e.g. cells of 2-8 kB). In a memory cell, electrons are taken out of the memory cell by an erase operation to make a threshold value voltage negative, and electrons are introduced into the memory cell by a write operation to set the threshold value voltage positive.
In order to increase the storage capacity of a NAND flash memory, a multi-bit memory that stores two or more bits in one cell has been developed. For example, in order to store two bits in one cell, four threshold value voltages are necessary to be set, and it is necessary to narrow the distribution of the threshold value voltages for one cell in comparison to a memory that stores one bit in one cell. Due to this, the write speed is lowered.
Also, if a neighboring cell is written by a coupling between neighboring cells through miniaturization of memory cells, the threshold value voltage of the cell first written is changed. Due to this, for example, a first memory cell is roughly written, a second memory cell, which is adjacent to the first memory cell, is roughly written, and then the threshold value voltage of the first memory cell is written as the original threshold value voltage. Also, a method has been performed, whereby the first memory cell is roughly written, the second memory cell, which is adjacent to the first memory cell, is roughly written, a third memory cell, which is adjacent to the second memory cell, (which is apart for two cells from the first memory cell) is roughly written, and then the original threshold value voltage is written in the first memory cell. By such a write method, the coupling between the neighboring cells is suppressed, and a plurality of threshold value voltages is set in one memory cell to make plural-bit storage possible.
However, the above-described write method has the problem that it is necessary to repeatedly perform the write operation up to several times with respect to one memory cell, and the write speed is low. Also, the increase in write frequency shortens the life span of the memory cell.
Accordingly, a write method, in which a multi-bit region MLB that includes multi-bit memory cells each storing two or more bits and a binary region SLB of memory cells each storing bits which are smaller than that of the multi-bit memory cell, for example, one bit, are installed, has been developed (for example, see Patent Document 1).
In this write method, data provided from the outside is first stored in SLB, and thereafter, the data in SLB is transferred to MLB to be stored as multi-bit data. Since high-speed writing is possible in SLB, the write speed can be heightened.
However, although the memory cells in SLB are frequently written, the memory cells in MLB have a smaller number of writings than that of the memory cells in SLB. Due to this, the memory cells in SLB deteriorate quickly in comparison to the memory cells in MLB. The deterioration of the memory cells causes performance deterioration of the NAND flash memory. Accordingly, in order to suppress the performance deterioration of the NAND flash memory and to realize high-speed writing, the storage capacity of SLB to the storage capacity of MLB has been considered. Specifically, if it is assumed that a memory cell in MLB stores two bits per cell, a memory cell in SLB stores one bit per cell, the number of rewritings in the memory cell in MLB is set to 1 k (k=1000), and the number of rewritings in the memory cell in SLB is set to 100 k, the memory cell in SLB has 100 times the number of rewritings of the memory cell in MLB, and thus it is sufficient if the number of blocks in SLB is 2% of the number of blocks in MLB.
However, if it is assumed that the number of rewritings in the memory cell in MLB is set to 1 k, and the number of rewritings in the memory cell in SLB is set to 50 k, it is necessary that SLB is 4% of MLB. Further, if it is assumed that the number of rewritings in the memory cell in MLB is set to 1 k, and the number of rewritings in the memory cell in SLB is set to 10 k, it is necessary that SLB is 20% of MLB. As described above, if the number of rewritings in SLB approximates the number of rewritings in MLB, a very large SLB is necessary in advance.